What Programs Use Multiple Cores

Microprocessor with more than than ane processing unit

Diagram of a generic dual-core processor with CPU-local level-1 caches and a shared, on-die level-2 enshroud

A multi-core processor is a figurer processor on a single integrated excursion with ii or more than separate processing units, called cores, each of which reads and executes program instructions.^[i] The instructions are ordinary CPU instructions (such equally add together, move information, and branch) only the single processor tin run instructions on split up cores at the same time, increasing overall speed for programs that support multithreading or other parallel computing techniques.^[2] Manufacturers typically integrate the cores onto a single integrated circuit die (known as a flake multiprocessor or CMP) or onto multiple dies in a single chip package. The microprocessors currently used in well-nigh all personal computers are multi-cadre.

A multi-core processor implements multiprocessing in a single concrete package. Designers may couple cores in a multi-core device tightly or loosely. For example, cores may or may not share caches, and they may implement bulletin passing or shared-retentiveness inter-core advice methods. Common network topologies used to interconnect cores include double-decker, ring, two-dimensional mesh, and crossbar. Homogeneous multi-core systems include only identical cores; heterogeneous multi-core systems have cores that are not identical (e.g. large.LITTLE accept heterogeneous cores that share the same instruction ready, while AMD Accelerated Processing Units have cores that practise not share the same instruction set up). Just as with unmarried-processor systems, cores in multi-core systems may implement architectures such as VLIW, superscalar, vector, or multithreading.

Multi-core processors are widely used across many application domains, including general-purpose, embedded, network, digital indicate processing (DSP), and graphics (GPU). Core count goes up to even dozens, and for specialized chips over 10,000,^[3] and in supercomputers (i.e. clusters of chips) the count can go over 10 million (and in one case upwardly to 20 one thousand thousand processing elements total in addition to host processors).^[iv]

The improvement in performance gained by the use of a multi-core processor depends very much on the software algorithms used and their implementation. In particular, possible gains are limited by the fraction of the software that can run in parallel simultaneously on multiple cores; this effect is described by Amdahl'south law. In the best case, so-chosen embarrassingly parallel issues may realize speedup factors near the number of cores, or even more if the problem is split up enough to fit within each cadre's cache(s), fugitive use of much slower main-system memory. Well-nigh applications, yet, are not accelerated equally much unless programmers invest effort in refactoring.^[5]

The parallelization of software is a significant ongoing topic of inquiry. Cointegration of multiprocessor applications provides flexibility in network compages pattern. Adjustability inside parallel models is an additional feature of systems utilizing these protocols.^[half-dozen]

Terminology [edit]

The terms multi-cadre and dual-core nearly commonly refer to some sort of central processing unit (CPU), simply are sometimes besides applied to digital signal processors (DSP) and system on a scrap (SoC). The terms are generally used just to refer to multi-core microprocessors that are manufactured on the same integrated circuit dice; split microprocessor dies in the aforementioned package are mostly referred to by another proper noun, such every bit multi-bit module. This commodity uses the terms "multi-core" and "dual-core" for CPUs manufactured on the same integrated circuit, unless otherwise noted.

In contrast to multi-core systems, the term multi-CPU refers to multiple physically dissever processing-units (which often contain special circuitry to facilitate communication between each other).

The terms many-core and massively multi-core are sometimes used to draw multi-core architectures with an particularly loftier number of cores (tens to thousands^[vii]).^[8]

Some systems use many soft microprocessor cores placed on a single FPGA. Each "cadre" tin can exist considered a "semiconductor intellectual property core" likewise as a CPU cadre.^{[ citation needed ]}

Development [edit]

While manufacturing applied science improves, reducing the size of individual gates, physical limits of semiconductor-based microelectronics have become a major design business organisation. These concrete limitations can crusade significant heat dissipation and data synchronization issues. Various other methods are used to improve CPU performance. Some instruction-level parallelism (ILP) methods such as superscalar pipelining are suitable for many applications, just are inefficient for others that contain difficult-to-predict code. Many applications are better suited to thread-level parallelism (TLP) methods, and multiple contained CPUs are normally used to increase a arrangement'southward overall TLP. A combination of increased available infinite (due to refined manufacturing processes) and the demand for increased TLP led to the development of multi-cadre CPUs.

Commercial incentives [edit]

Several business motives drive the development of multi-core architectures. For decades, information technology was possible to improve performance of a CPU by shrinking the area of the integrated excursion (IC), which reduced the price per device on the IC. Alternatively, for the same circuit area, more than transistors could be used in the design, which increased functionality, especially for complex education set computing (CISC) architectures. Clock rates as well increased by orders of magnitude in the decades of the late 20th century, from several megahertz in the 1980s to several gigahertz in the early 2000s.

As the rate of clock speed improvements slowed, increased utilise of parallel calculating in the class of multi-cadre processors has been pursued to improve overall processing performance. Multiple cores were used on the aforementioned CPU flake, which could then atomic number 82 to better sales of CPU chips with two or more cores. For example, Intel has produced a 48-core processor for research in deject calculating; each core has an x86 architecture.^{[9] [10]}

Technical factors [edit]

Since computer manufacturers have long implemented symmetric multiprocessing (SMP) designs using discrete CPUs, the problems regarding implementing multi-cadre processor architecture and supporting it with software are well known.

Additionally:

• Using a proven processing-core design without architectural changes reduces design adventure significantly.
• For general-purpose processors, much of the motivation for multi-core processors comes from profoundly diminished gains in processor operation from increasing the operating frequency. This is due to three primary factors:^[11]
  1. The retention wall; the increasing gap between processor and retentiveness speeds. This, in effect, pushes for cache sizes to exist larger in gild to mask the latency of memory. This helps only to the extent that memory bandwidth is not the clogging in performance.
  2. The ILP wall; the increasing difficulty of finding enough parallelism in a unmarried educational activity stream to keep a high-performance single-core processor busy.
  3. The power wall; the tendency of consuming exponentially increasing ability (and thus also generating exponentially increasing heat) with each factorial increment of operating frequency. This increment can be mitigated by "shrinking" the processor by using smaller traces for the same logic. The power wall poses manufacturing, organization pattern and deployment problems that have not been justified in the face of the macerated gains in functioning due to the memory wall and ILP wall.^{[ citation needed ]}

In order to go along delivering regular performance improvements for general-purpose processors, manufacturers such as Intel and AMD have turned to multi-cadre designs, sacrificing lower manufacturing-costs for college functioning in some applications and systems. Multi-core architectures are existence developed, but and so are the alternatives. An especially strong contender for established markets is the further integration of peripheral functions into the chip.

Advantages [edit]

The proximity of multiple CPU cores on the aforementioned dice allows the cache coherency circuitry to operate at a much college clock rate than what is possible if the signals take to travel off-fleck. Combining equivalent CPUs on a single die significantly improves the functioning of cache snoop (alternative: Bus snooping) operations. Put simply, this means that signals between different CPUs travel shorter distances, and therefore those signals degrade less. These higher-quality signals permit more data to be sent in a given fourth dimension flow, since individual signals can be shorter and do not demand to exist repeated as often.

Assuming that the die tin physically fit into the package, multi-cadre CPU designs require much less printed excursion board (PCB) infinite than do multi-chip SMP designs. Also, a dual-cadre processor uses slightly less ability than ii coupled single-cadre processors, principally because of the decreased power required to drive signals external to the chip. Furthermore, the cores share some circuitry, like the L2 enshroud and the interface to the front-side omnibus (FSB). In terms of competing technologies for the available silicon dice area, multi-cadre design tin make use of proven CPU core library designs and produce a production with lower take chances of design fault than devising a new wider-core design. Too, calculation more cache suffers from diminishing returns.

Multi-cadre chips also allow higher performance at lower free energy. This can exist a large cistron in mobile devices that operate on batteries. Since each core in a multi-core CPU is generally more than energy-efficient, the scrap becomes more efficient than having a single large monolithic core. This allows higher performance with less energy. A challenge in this, nonetheless, is the additional overhead of writing parallel code.^[12]

Disadvantages [edit]

Maximizing the usage of the computing resources provided by multi-core processors requires adjustments both to the operating system (OS) support and to existing application software. Also, the ability of multi-cadre processors to increase application performance depends on the use of multiple threads within applications.

Integration of a multi-cadre chip tin lower the fleck production yields. They are also more difficult to manage thermally than lower-density single-cadre designs. Intel has partially countered this first problem by creating its quad-core designs by combining two dual-core ones on a unmarried die with a unified cache, hence any 2 working dual-core dies can be used, equally opposed to producing four cores on a unmarried die and requiring all four to work to produce a quad-core CPU. From an architectural point of view, ultimately, unmarried CPU designs may make better use of the silicon surface surface area than multiprocessing cores, and so a development commitment to this architecture may carry the risk of obsolescence. Finally, raw processing power is non the only constraint on arrangement performance. Two processing cores sharing the aforementioned system bus and memory bandwidth limits the real-globe performance advantage. In a 2009 report, Dr Jun Ni showed that if a single core is close to being memory-bandwidth limited, then going to dual-core might requite 30% to 70% improvement; if retentiveness bandwidth is not a problem, so a 90% improvement can be expected; notwithstanding, Amdahl'due south law makes this merits dubious.^[13] It would be possible for an application that used two CPUs to cease upward running faster on a single-core one if communication betwixt the CPUs was the limiting cistron, which would count as more than 100% improvement.

Hardware [edit]

Trends [edit]

The tendency in processor development has been towards an ever-increasing number of cores, as processors with hundreds or even thousands of cores go theoretically possible.^[14] In improver, multi-core fries mixed with simultaneous multithreading, retentivity-on-fleck, and special-purpose "heterogeneous" (or disproportionate) cores promise further performance and efficiency gains, especially in processing multimedia, recognition and networking applications. For example, a big.LITTLE core includes a high-performance core (called 'big') and a low-power core (chosen 'LITTLE'). There is also a trend towards improving energy-efficiency by focusing on operation-per-watt with advanced fine-grain or ultra fine-grain power management and dynamic voltage and frequency scaling (i.e. laptop computers and portable media players).

Fries designed from the start for a large number of cores (rather than having evolved from single core designs) are sometimes referred to every bit manycore designs, emphasising qualitative differences.

Architecture [edit]

The composition and balance of the cores in multi-cadre architecture evidence great variety. Some architectures utilize one core design repeated consistently ("homogeneous"), while others use a mixture of different cores, each optimized for a dissimilar, "heterogeneous" function.

How multiple cores are implemented and integrated significantly affects both the developer'south programming skills and the consumer'due south expectations of apps and interactivity versus the device.^[15] A device advertised as existence octa-cadre will just take independent cores if advertised as Truthful Octa-core, or similar styling, as opposed to being just 2 sets of quad-cores each with fixed clock speeds.^{[16] [17]}

The article "CPU designers debate multi-core future" by Rick Merritt, EE Times 2008,^[18] includes these comments:

Chuck Moore [...] suggested computers should be like cellphones, using a multifariousness of specialty cores to run modular software scheduled past a high-level applications programming interface.

[...] Atsushi Hasegawa, a senior chief engineer at Renesas, mostly agreed. He suggested the cellphone'due south utilize of many specialty cores working in concert is a skillful model for time to come multi-core designs.

[...] Anant Agarwal, founder and chief executive of startup Tilera, took the opposing view. He said multi-core chips need to exist homogeneous collections of general-purpose cores to go along the software model simple.

Software furnishings [edit]

An outdated version of an anti-virus application may create a new thread for a scan process, while its GUI thread waits for commands from the user (e.g. cancel the scan). In such cases, a multi-core architecture is of little benefit for the awarding itself due to the unmarried thread doing all the heavy lifting and the inability to rest the piece of work evenly across multiple cores. Programming truly multithreaded code often requires complex co-ordination of threads and can easily introduce subtle and difficult-to-find bugs due to the interweaving of processing on data shared between threads (come across thread-prophylactic). Consequently, such code is much more difficult to debug than single-threaded code when it breaks. There has been a perceived lack of motivation for writing consumer-level threaded applications because of the relative rarity of consumer-level demand for maximum use of calculator hardware. Besides, serial tasks like decoding the entropy encoding algorithms used in video codecs are incommunicable to parallelize because each result generated is used to help create the next result of the entropy decoding algorithm.

Given the increasing accent on multi-core chip design, stemming from the grave thermal and ability consumption issues posed by whatever further significant increase in processor clock speeds, the extent to which software can be multithreaded to take advantage of these new chips is likely to exist the unmarried greatest constraint on computer performance in the hereafter. If developers are unable to blueprint software to fully exploit the resources provided by multiple cores, then they will ultimately reach an insurmountable performance ceiling.

The telecommunication market had been one of the first that needed a new design of parallel datapath packet processing because there was a very quick adoption of these multiple-cadre processors for the datapath and the control airplane. These MPUs are going to replace^[19] the traditional Network Processors that were based on proprietary microcode or picocode.

Parallel programming techniques can do good from multiple cores directly. Some existing parallel programming models such as Cilk Plus, OpenMP, OpenHMPP, FastFlow, Skandium, MPI, and Erlang tin be used on multi-core platforms. Intel introduced a new brainchild for C++ parallelism called TBB. Other research efforts include the Codeplay Sieve System, Cray'due south Chapel, Sun'due south Fortress, and IBM's X10.

Multi-core processing has also affected the power of modern computational software development. Developers programming in newer languages might find that their modern languages do not support multi-core functionality. This then requires the utilise of numerical libraries to access code written in languages like C and Fortran, which perform math computations faster than newer languages like C#. Intel's MKL and AMD's ACML are written in these native languages and take advantage of multi-core processing. Balancing the application workload across processors can be problematic, especially if they take different operation characteristics. There are unlike conceptual models to deal with the trouble, for example using a coordination language and program building blocks (programming libraries or higher-club functions). Each block can have a different native implementation for each processor type. Users only program using these abstractions and an intelligent compiler chooses the best implementation based on the context.^[20]

Managing concurrency acquires a central role in developing parallel applications. The basic steps in designing parallel applications are:

Segmentation

The partitioning stage of a design is intended to expose opportunities for parallel execution. Hence, the focus is on defining a large number of small tasks in order to yield what is termed a fine-grained decomposition of a problem.

Communication

The tasks generated by a partition are intended to execute meantime just cannot, in full general, execute independently. The ciphering to be performed in one task will typically require data associated with some other task. Data must then be transferred between tasks then as to allow computation to proceed. This information menstruum is specified in the communication stage of a pattern.

Bunch

In the third stage, development moves from the abstract toward the concrete. Developers revisit decisions fabricated in the partitioning and communication phases with a view to obtaining an algorithm that will execute efficiently on some class of parallel computer. In particular, developers consider whether it is useful to combine, or agglomerate, tasks identified by the partitioning stage, so as to provide a smaller number of tasks, each of greater size. They also determine whether information technology is worthwhile to replicate data and computation.

Mapping

In the fourth and final stage of the design of parallel algorithms, the developers specify where each job is to execute. This mapping problem does non arise on uniprocessors or on shared-retentivity computers that provide automated task scheduling.

On the other hand, on the server side, multi-core processors are platonic because they allow many users to connect to a site simultaneously and have independent threads of execution. This allows for Web servers and awarding servers that accept much improve throughput.

Licensing [edit]

Vendors may license some software "per processor". This can give rise to ambiguity, because a "processor" may consist either of a single cadre or of a combination of cores.

• Initially, for some of its enterprise software, Microsoft continued to employ a per-socket licensing system. Withal, for some software such every bit BizTalk Server 2013, SQL Server 2014, and Windows Server 2016, Microsoft has shifted to per-core licensing.^[21]
• Oracle Corporation counts an AMD X2 or an Intel dual-core CPU as a single processor^{[ citation needed ]} but uses other metrics for other types, especially for processors with more than two cores.^[22]

Embedded applications [edit]

An embedded system on a plug-in card with processor, retentivity, ability supply, and external interfaces

Embedded computing operates in an surface area of processor technology distinct from that of "mainstream" PCs. The same technological drives towards multi-core use hither too. Indeed, in many cases the application is a "natural" fit for multi-core technologies, if the task can easily be partitioned between the different processors.

In add-on, embedded software is typically developed for a specific hardware release, making issues of software portability, legacy code or supporting contained developers less critical than is the example for PC or enterprise calculating. As a upshot, it is easier for developers to prefer new technologies and as a result there is a greater variety of multi-core processing architectures and suppliers.

Network processors [edit]

Every bit of 2010^[update], multi-core network processors have become mainstream, with companies such every bit Freescale Semiconductor, Cavium Networks, Wintegra and Broadcom all manufacturing products with viii processors. For the system developer, a key claiming is how to exploit all the cores in these devices to accomplish maximum networking performance at the system level, despite the functioning limitations inherent in a symmetric multiprocessing (SMP) operating organization. Companies such as 6WIND provide portable parcel processing software designed then that the networking data plane runs in a fast path environment exterior the operating system of the network device.^[23]

Digital signal processing [edit]

In digital signal processing the same trend applies: Texas Instruments has the 3-cadre TMS320C6488 and four-core TMS320C5441, Freescale the four-cadre MSC8144 and 6-cadre MSC8156 (and both have stated they are working on eight-cadre successors). Newer entries include the Storm-1 family from Stream Processors, Inc with xl and 80 general purpose ALUs per fleck, all programmable in C every bit a SIMD engine and Picochip with 300 processors on a single die, focused on advice applications.

Heterogeneous systems [edit]

In heterogeneous calculating, where a system uses more than one kind of processor or cores, multi-core solutions are becoming more common: Xilinx Zynq UltraScale+ MPSoC has a quad-cadre ARM Cortex-A53 and dual-core ARM Cortex-R5. Software solutions such every bit OpenAMP are beingness used to help with inter-processor communication.

Mobile devices may use the ARM big.Piffling architecture.

Hardware examples [edit]

Commercial [edit]

• Adapteva Epiphany, a many-core processor compages which allows up to 4096 processors on-chip, although only a sixteen core version has been commercially produced.
• Aeroflex Gaisler LEON3, a multi-core SPARC that too exists in a fault-tolerant version.
• Ageia PhysX, a multi-cadre physics processing unit.
• Ambric Am2045, a 336-cadre Massively Parallel Processor Array (MPPA)
• AMD
  • A-Series, dual-, triple-, and quad-cadre of Accelerated Processor Units (APU).
  • Athlon 64 FX and Athlon 64 X2 single- and dual-core desktop processors.
  • Athlon Two, dual-, triple-, and quad-core desktop processors.
  • FX-Series, quad-, 6-, and 8-core desktop processors.
  • Opteron, unmarried-, dual-, quad-, vi-, 8-, 12-, and 16-core server/workstation processors.
  • Phenom, dual-, triple-, and quad-core processors.
  • Phenom II, dual-, triple-, quad-, and 6-core desktop processors.
  • Sempron, single-, dual-, and quad-core entry level processors.^[24]
  • Turion, unmarried- and dual-core laptop processors.
  • Ryzen, dual-, quad-, 6-, viii-, 12-, xvi-, 24-, 32-, and 64-core desktop, mobile, and embedded platform processors.
  • Epyc, quad-, viii-, 12-, 16-, 24-, 32-, and 64-core server and embedded processors.
  • Radeon and FireStream multi-core GPU/GPGPU (x cores, sixteen five-effect wide superscalar stream processors per core).
• Analog Devices Blackfin BF561, a symmetrical dual-cadre processor
• ARM MPCore is a fully synthesizable multi-core container for ARM11 MPCore and ARM Cortex-A9 MPCore processor cores, intended for loftier-performance embedded and entertainment applications.
• ASOCS ModemX, up to 128 cores, wireless applications.
• Azul Systems
  • Vega 1, a 24-core processor, released in 2005.
  • Vega ii, a 48-cadre processor, released in 2006.
  • Vega 3, a 54-cadre processor, released in 2008.
• Broadcom SiByte SB1250, SB1255, SB1455; BCM 2836 quad-cadre ARM SoC (designed for the Raspberry Pi ii)
• Cadence Design Systems Tensilica Xtensa LX6, bachelor in a dual-core configuration in Espressif Systems's ESP32
• ClearSpeed
  • CSX700, 192-core processor, released in 2008 (32/64-fleck floating point; Integer ALU).
• Cradle Technologies CT3400 and CT3600, both multi-core DSPs.
• Cavium Networks Octeon, a 32-core MIPS MPU.
• Coherent Logix hx3100 Processor, a 100-core DSP/GPP processor.
• Freescale Semiconductor QorIQ series processors, upwardly to 8 cores, Power ISA MPU.
• Hewlett-Packard PA-8800 and PA-8900, dual core PA-RISC processors.
• IBM
  • POWER4, a dual-core PowerPC processor, released in 2001.
  • POWER5, a dual-core PowerPC processor, released in 2004.
  • POWER6, a dual-core PowerPC processor, released in 2007.
  • POWER7, a 4,6,8-core PowerPC processor, released in 2010.
  • POWER8, a 12-core PowerPC processor, released in 2013.
  • POWER9, a 12 or 24-core PowerPC processor, released in 2017.
  • Power10, a 15 or 30-core PowerPC processor, released in 2021.
  • PowerPC 970MP, a dual-core PowerPC processor, used in the Apple tree Power Mac G5.
  • Xenon, a triple-core, SMT-capable, PowerPC microprocessor used in the Microsoft Xbox 360 game console.
  • z10, a quad-core z/Architecture processor, released in 2008.
  • z196, a quad-core z/Architecture processor, released in 2010.
  • zEC12, a six-core z/Architecture processor, released in 2012.
  • z13, an viii-core z/Compages processor, released in 2015.
  • z14, a ten-core z/Architecture processor, released in 2017.
  • z15, a twelve-core z/Architecture processor, released in 2019.
  • Telum, an viii-cadre z/Architecture processor, released in 2021.

• Infineon
  • AURIX
  • Danube, a dual-core, MIPS-based, home gateway processor.
• Intel
  • Atom, single, dual-core, quad-cadre, 8-, 12-, and 16-core processors for netbooks, nettops, embedded applications, and mobile internet devices (MIDs).^[25]
  • Atom SoC (organisation on a bit), single-core, dual-cadre, and quad-cadre processors for smartphones and tablets.^[26]
  • Celeron, the kickoff dual-core (and, later, quad-core) processor for the upkeep/entry-level market.^{[27] [28]}
  • Core Duo, a dual-core processor.^[29]
  • Core 2 Duo, a dual-core processor.^[xxx]
  • Cadre 2 Quad, two dual-cadre dies packaged in a multi-fleck module.^[31]
  • Core i3, Core i5, Core i7 and Core i9, a family of dual-, quad-, 6-, 8-, 10-, 12-, fourteen-, 16-, and xviii-cadre processors, and the successor of the Core 2 Duo and the Core ii Quad.^[32]
  • Itanium, single, dual-core, quad-core, and 8-core processors.^[33]
  • Pentium, single, dual-core, and quad-cadre processors for the entry-level market.^[34]
  • Teraflops Research Chip (Polaris), a iii.sixteen GHz, fourscore-core processor image, which the company originally stated would be released by 2011.^[35]
  • Xeon dual-, quad-, vi-, 8-, 10-, 12-, 14-, 15-, sixteen-, 18-, 20-, 22-, 24-, 26-, 28-, 32-, 48-, and 56-core processors.^{[36] [37] [38] [39] [forty] [41]}
  • Xeon Phi 57-, sixty-, 61-, 64-, 68-, and 72-core processors.^{[42] [43]}
• IntellaSys
  • SEAforth 40C18, a 40-core processor.^[44]
  • SEAforth24, a 24-core processor designed by Charles H. Moore.
• Kalray
  • MPPA-256, 256-core processor, released 2012 (256 usable VLIW cores, Network-on-Chip (NoC), 32/64-chip IEEE 754 compliant FPU)
• NetLogic Microsystems
  • XLP, a 32-core, quad-threaded MIPS64 processor.
  • XLR, an eight-cadre, quad-threaded MIPS64 processor.
  • XLS, an eight-cadre, quad-threaded MIPS64 processor.
• Nvidia
  • GeForce nine multi-cadre GPU (eight cores, sixteen scalar stream processors per core).
  • GeForce 200 multi-cadre GPU (10 cores, 24 scalar stream processors per cadre).
  • Tesla multi-cadre GPGPU (ten cores, 24 scalar stream processors per cadre).
  • RTX 3090 (10496 CUDA cores, GPGPU cores;^[3] plus other more than specialized cores).
• Parallax Propeller P8X32, an eight-core microcontroller.
• picoChip PC200 series 200–300 cores per device for DSP & wireless.
• Plurality HAL serial tightly coupled 16-256 cores, L1 shared memory, hardware synchronized processor.
• Rapport Kilocore KC256, a 257-core microcontroller with a PowerPC core and 256 8-flake "processing elements".
• SiCortex "SiCortex node" has six MIPS64 cores on a single chip.
• Sony/IBM/Toshiba'due south Prison cell processor, a 9-core processor with one general purpose PowerPC cadre and eight specialized SPUs (Synergistic Processing Unit) optimized for vector operations used in the Sony PlayStation 3.
• Dominicus Microsystems
  • MAJC 5200, ii-core VLIW processor.
  • UltraSPARC IV and UltraSPARC Iv+, dual-core processors.
  • UltraSPARC T1, an eight-core, 32-thread processor.
  • UltraSPARC T2, an eight-core, 64-concurrent-thread processor.
  • UltraSPARC T3, a sixteen-core, 128-concurrent-thread processor.
  • SPARC T4, an 8-core, 64-concurrent-thread processor.
  • SPARC T5, a 16-cadre, 128-concurrent-thread processor.
• Sunway
  • Sunway SW26010, a 260-core processor used in the Sunway TaihuLight.
• Texas Instruments
  • TMS320C80 MVP, a five-core multimedia video processor.
  • TMS320TMS320C66, 2,4,8 core DSP.
• Tilera
  • TILE64, a 64-core 32-bit processor.
  • TILE-Gx, a 72-core 64-scrap processor.
• XMOS Software Defined Silicon quad-core XS1-G4.

Free [edit]

• OpenSPARC

Academic [edit]

• MIT, 16-core RAW processor
• University of California, Davis, Asynchronous assortment of simple processors (AsAP)
  • 36-core 610 MHz AsAP
  • 167-core 1.2 GHz AsAP2
• University of Washington, Wavescalar processor
• Academy of Texas, Austin, TRIPS processor
• Linköping University, Sweden, ePUMA processor
• UC Davis, Kilocore, a m cadre one.78 GHz processor on a 32 nm IBM process^[45]

Benchmarks [edit]

The research and development of multicore processors oftentimes compares many options, and benchmarks are adult to help such evaluations. Existing benchmarks include SPLASH-2, PARSEC, and Catholic for heterogeneous systems.^[46]

See as well [edit]

• CPU shielding
• CUDA
• GPGPU
• Hyper-threading
• Manycore
• Multicore Clan
• Multitasking
• OpenCL (Open up Computing Linguistic communication) – a framework for heterogeneous execution
• Parallel random access machine
• Partitioned global address infinite (PGAS)
• Race status
• Thread

Notes [edit]

1. ^ Digital signal processors (DSPs) have used multi-core architectures for much longer than high-end general-purpose processors. A typical example of a DSP-specific implementation would be a combination of a RISC CPU and a DSP MPU. This allows for the design of products that crave a full general-purpose processor for user interfaces and a DSP for existent-time data processing; this type of pattern is common in mobile phones. In other applications, a growing number of companies take developed multi-cadre DSPs with very big numbers of processors.
2. ^ Two types of operating systems are able to apply a dual-CPU multiprocessor: partitioned multiprocessing and symmetric multiprocessing (SMP). In a partitioned architecture, each CPU boots into separate segments of concrete memory and operate independently; in an SMP OS, processors work in a shared space, executing threads inside the Os independently.

References [edit]

1. ^ Rouse, Margaret (March 27, 2007). "Definition: multi-core processor". TechTarget. Archived from the original on Baronial v, 2010. Retrieved March 6, 2013.
2. ^ Schauer, Bryan. "Multicore Processors – A Necessity" (PDF). Archived from the original (PDF) on 2011-eleven-25.
3. ^ ^{a b} Smith, Ryan. "NVIDIA Announces the GeForce RTX 30 Series: Ampere For Gaming, Starting With RTX 3080 & RTX 3090". www.anandtech.com . Retrieved 2020-09-xv .
4. ^ "Sunway TaihuLight - Sunway MPP, Sunway SW26010 260C one.45GHz, Sunway | TOP500". www.top500.org . Retrieved 2020-09-fifteen .
5. ^ Suleman, Aater (May 20, 2011). "What makes parallel programming hard?". FutureChips. Archived from the original on May 29, 2011. Retrieved March 6, 2013.
6. ^ Duran, A (2011). "Ompss: a proposal for programming heterogeneous multi-core architectures". Parallel Processing Messages. 21 (2): 173–193. doi:ten.1142/S0129626411000151.
7. ^ Schor, David (November 2017). "The 2,048-cadre PEZY-SC2 sets a Green500 tape". WikiChip.
8. ^ Vajda, András (2011-06-10). Programming Many-Cadre Chips. Springer. p. 3. ISBN978-i-4419-9739-five.
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Farther reading [edit]

• Khondker S. Hasan, Nicolas 1000. Grounds, John K. Antonio (July 2011). Predicting CPU Availability of a Multi-core Processor Executing Concurrent Java Threads. 17th International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA-11). Las Vegas, Nevada, USA. pp. 551–557. {{cite conference}}: CS1 maint: uses authors parameter (link)
• Khondker South. Hasan, John Antonio, Sridhar Radhakrishnan (February 2014). A New Composite CPU/Memory Model for Predicting Efficiency of Multi-core Processing. The 20th IEEE International Conference on High Operation Figurer Architecture (HPCA-xiv) workshop. Orlando, FL, The states. doi:10.13140/RG.2.1.3051.9207. {{cite briefing}}: CS1 maint: uses authors parameter (link)

External links [edit]

• "What Is a Processor Core?"—MakeUseOf
• "Embedded moves to multicore"—Embedded Computing Design
• "Multicore Is Bad News for Supercomputers"—IEEE Spectrum
• Architecting solutions for the Manycore hereafter, published on Feb 19, 2010 (more than one dead link in the slide)

What Programs Use Multiple Cores,

Source: https://en.wikipedia.org/wiki/Multi-core_processor

Posted by: morelandshrem1977.blogspot.com

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